dsPIC33AK support
The dsPIC33AK series from Microchip Technology represents a significant advancement in Digital Signal Controllers (DSCs), combining high-performance processing with robust peripheral integration.
📌 Key features
| Feature |
dsPIC33AK |
| Core |
32-bits |
| Performance |
200 DMIPS |
| Program memory |
32-512 KB |
| Data memory |
8-64 KB |
| Pin count |
28-100 |
🧩 Peripheral overview
| Peripheral |
UART |
TMR |
OC |
IC |
I2C |
SPI |
CAN |
SENT |
CLC |
QEI |
PWM |
MCCP |
SCCP |
| MC10X |
3 |
1 |
0 |
0 |
2 |
3 |
0 |
2 |
4 |
1 |
4 |
0 |
4 |
| MC2XX |
3 |
3 |
0 |
0 |
3 |
4 |
0 |
2 |
10 |
4 |
12 |
1 |
8 |
| MC5XX |
3 |
3 |
0 |
0 |
3 |
4 |
2 Fd |
2 |
10 |
4 |
12 |
1 |
8 |
| MPS2XX |
3 |
3 |
0 |
0 |
3 |
4 |
0 |
2 |
10 |
4 |
12 |
1 |
8 |
| MPS5XX |
3 |
3 |
0 |
0 |
3 |
4 |
2 Fd |
2 |
10 |
4 |
12 |
1 |
8 |
📦 Device list
48 devices on May 2025.
MC10X subfamily
Base device.
MC2XX subfamily
MP10X with more peripherals and memory :
- 2 more timer
- 1 more SPI
- 6 more CLC
- 3 more QEI
- 8 more PWM
- 3 more ADC modules
- 5 more MCCP/SCCP modules
- Internal core is generated from an integrated buck
⚠️ Note: Need additionnal inductor and capacitor for internal buck (4 pins are dedicated to buck).
MC5XX subfamily
MC2XX with 2 CAN Fd.
MPS2XX subfamily
MC2XX with crypto accelerator and all PWM as fast PWM.
MPS5XX subfamily
MPS2XX with 2 CAN Fd.
📚 Comparison with dsPIC33CK/CH Family
| Feature |
dsPIC33CK |
dsPIC33AK |
| Core speed |
100 MHz |
200 MHz |
| Pipeline stages |
1-stage |
5-stage |
| Working registers |
16 x 16-bit |
16 x 32-bit |
| Accumulators |
2 x 40-bit |
2 x 72-bit |
| Alternate register contexts |
4 |
7 |
| FPU |
None |
Yes (64 bits) |
sysclock
| Feature |
dsPIC33CK |
dsPIC33AK |
| Clock Sources |
Up to 5 |
Up to 6 |
| PLL Generators |
2 |
2 |
| Clock Generators |
- |
Up to 16 |
| Fractional Dividers |
1 global |
1 per generator |
| Backup Clock Sources |
Fixed |
Configurable |
| Fail Safe Clock Monitor |
1 global |
1 per generator |
| Fault Injection |
- |
1 per generator |
| Clock Monitors |
- |
Up to 4 |
ADC
| Feature |
dsPIC33CK |
dsPIC33AK |
| Number of Analog Conversion |
Cores 3-5 cores, 3.5 MSPS |
2-5 cores, 40 MSPS |
| Maximum Signal Source Impedance |
(200 ns Sampling Time) |
1 kOhm, CHold = ~ 16pF 22 kOhms, Chold = ~1 pF |
| Sampling Time Selection |
Same for all core channels |
Selectable for each input |
| Inputs Conversion Priority/Order |
Fixed |
Programmable |
| Conversion Result Comparators |
Typically 4 |
Up to 20 (1 per channel) |
| Result Accumulators |
Typically 4 |
Up to 20 (1 per channel) |
| Trigger Selection |
Set for each input |
Set for each channel |